1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, especially a semiconductor device with an offset sidewall structure.
2. Description of the Background Art
In conventional semiconductor devices, impurity ion implantation is performed with gate electrodes as implant masks thereby to form extension layers in a self-aligned manner. The extension layers here are impurity layers which are formed to produce shallower junctions than main source/drain layers later to be formed. The extension layers are of the same conductivity type as the main source/drain layers and function as source/drain layers; thus, they should be referred to as source/drain extension layers but for convenience's sake, they are referred to herein as the extension layers.
In this method, however, the extension layers extend more than necessary under the gate electrodes due to scattering of impurity ions during implantation and diffusion of impurity ions in a subsequent process. This is shown in FIG. 34.
In a MOS transistor M1 shown in FIG. 34, a gate insulating film GX is selectively formed on a semiconductor substrate SB and a gate electrode GT is formed on the gate insulating film GX. In the surface of the semiconductor substrate SB on both sides of the gate electrode GT, a pair of extension layers EX are formed extending under the gate electrode GT. This state is called a gate overlap. In the case of FIG. 34, a gate overlap length of each extension layer EX is represented by L1. As shown, excessive extension of the extension layers EX under the gate electrode GT reduces an effective channel length (L2), thereby making a short channel effect more prominent.
In recent semiconductor devices with minimum gate lengths of less than 0.1 μm, a short channel effect becomes more prominent and a slight reduction of the gate length from the design value will interfere with transistor operation. That is, the short channel effect has become the leading cause of low manufacturing yield. The gate overlap, which brings about a short channel effect, is thus an undesirable phenomenon.
FIG. 35 illustrates in schematic form the MOS transistor M1 in standby mode. As shown in FIG. 35, during standby, a voltage of 0V is applied to the extension layer EX on the source side, a voltage of 1V to the extension layer EX on the drain side and a voltage of 0V to the gate electrode GT and the semiconductor substrate SB. In this case, a leakage current flows between the gate and the drain in proportion to the area of gate-to-drain overlap. In gate insulating films with recent noticeable tendencies of thin film thickness, gate overlaps produce a more prominent gate-drain current leakage, thereby becoming a factor of increase in standby power of LSIs.
FIG. 36 illustrates in schematic form the MOS transistor M1 in operation mode. As shown in FIG. 36, during operation, a voltage of 0V is applied to the extension layer EX on the source side and a voltage of 0 to 1 V to the extension layer EX on the drain side and to the gate electrode GT. The gate and drain voltages may vary in actual circuit operation, in which case a large area of gate overlap causes an increase in parasitic capacitance and requires a greater amount of charge to be applied thereto, thus becoming a big factor of delay in circuit operation.
To eliminate these problems, offset sidewall structures have recently been adopted. FIG. 37 shows one example of an offset sidewall structure. In FIG. 37, like components to those of the MOS transistor M1 shown in FIG. 34 are designated by the same reference numerals and will not be described herein.
Referring to FIG. 37, an offset sidewall OF is formed adjacent to the side surfaces of the gate electrode GT and the gate insulating film GX. After the formation of the offset sidewall OF, the extension layers EX are formed in a self-aligned manner, using the gate electrode GT and the offset sidewall OF as implant masks. Thereby the lengths of the extension layers EX extending under the gate electrode GT can be reduced.
In this method, however, the following inconvenience occurs in semiconductor devices with both N-channel MOS transistors (NMOS transistors) and P-channel MOS transistors (PMOS transistors).
FIG. 38 shows an NMOS transistor M11 and a PMOS transistor M12 formed on the same semiconductor substrate SB.
Referring to FIG. 38, the NMOS transistor M11 comprises a gate insulating film GX1 selectively formed on the semiconductor substrate SB, a gate electrode GT1 formed on the gate insulating film GX1, an offset sidewall OF1 formed adjacent to the side surfaces of the gate electrode GT1 and the gate insulating film GX1, and a pair of extension layers EX1 formed in the surface of the semiconductor substrate SB on both sides of the gate electrode GT1. In this case, the gate overlap lengths of the extension layers EX1 are represented by L3 and an effective channel length is represented by L4.
The PMOS transistor M12 comprises a gate insulating film GX2 selectively formed on the semiconductor substrate SB, a gate electrode GT2 formed on the gate insulating film GX2, an offset sidewall OF2 formed adjacent to the side surfaces of the gate electrode GT2 and the gate insulating film GX2, and a pair of extension layers EX2 formed in the surface of the semiconductor substrate SB on both sides of the gate electrode GT2. In this case, the gate overlap lengths of the extension layers EX2 are represented by L5 and an effective channel length is represented by L6.
A comparison between the NMOS transistor M11 and the PMOS transistor M12 indicates that the gate overlap length L3 of the NMOS transistor M11 is shorter than the gate overlap length L5 of the PMOS transistor M12 and thus, the effective channel length L4 is longer than L6.
This is because boron (B) which is generally used as source and drain impurities for PMOS transistors has a much higher diffusion rate within silicon than arsenic (As) which is generally used as source and drain impurities for NMOS transistors.
That is, even if ion implantations of As and B produce implanted layers of the same shape, B will diffuse more widely in a subsequent heat treatment process and thereby the extension layers EX2 of the PMOS transistor M12 have a greater gate overlap length than the extension layers EX1 of the NMOS transistor M11.
This results in a more prominent short channel effect of the PMOS transistor M12, an increase in gate-drain parasitic capacitance, and an increase in gate-drain current leakage.
FIG. 39 illustrates an NMOS transistor (NMOSFET) M21 and a PMOS transistor (PMOSFET) M22 formed on the same semiconductor substrate SB. These transistors M21 and M22 differ from the NMOS transistor M11 and the PMOS transistor M12 of FIG. 38 in that their respective offset sidewalls OF11 and OF 12 are greater in width than the offset sidewalls OF1 and OF2, respectively.
By expanding the width of the offset sidewall, the PMOS transistor M22 can have a shorter gate overlap length and a longer effective channel length. In the NMOS transistor M21, however, because of the expanded width of the offset sidewall OF11, doped impurities cannot extend under the gate electrode GT1 even by heat treatment during process, no gate overlaps occur, and thus isolation is established between the source and drain of the NMOS transistor M21, thereby causing a reduction in operating current.
Now, as one example of a conventional method of manufacturing a semiconductor device with both NMOS and PMOS transistors, a method of manufacturing a semiconductor device with CMOS transistors 90A and 90B will be described with reference to FIGS. 40 through 46, which are cross-sectional views illustrating the manufacturing process step by step. The CMOS transistor 90A is low-voltage compliant and the CMOS transistor 90B is high-voltage compliant, their respective structures being illustrated in the final step of FIG. 46.
Referring first to FIG. 40, an element isolation insulating film 2 is selectively formed in the surface of a silicon substrate 1 to define a low-voltage NMOS region LNR for forming a low-voltage NMOS transistor, a low-voltage PMOS region LPR for forming a low-voltage PMOS transistor, a high-voltage NMOS region HNR for forming a high-voltage NMOS transistor and a high-voltage PMOS region HPR for forming a high-voltage PMOS transistor. The low-voltage NMOS and PMOS regions LNR and LPR may generically be referred to as a low-voltage circuit portion, and the high-voltage NMOS and PMOS regions HNR and HPR may generically be referred to as a high-voltage circuit portion.
In the surface of the silicon substrate 1, P-well regions PW containing P-type impurities are formed corresponding to the low-voltage NMOS region LNR and the high-voltage NMOS region HNR, and N-well regions NW containing N-type impurities are formed corresponding to the low-voltage PMOS region LPR and the high-voltage PMOS region HPR. In the following description, the P-well regions PW and the N-well regions NW may be simply referred to as the silicon substrate without distinction.
Then, a first insulation film such as silicon oxide film is formed to a first thickness to cover the whole surface of the silicon substrate 1. After that, a resist mask is formed to expose the low-voltage circuit portion and the first insulation film is removed from the low-voltage circuit portion by, for example, hydrofluoric acid treatment.
The resist mask is then removed and a second insulation film such as silicon oxide film is formed to a second thickness to cover the whole surface of the silicon substrate 1. Thereby the low-voltage circuit portion has an insulation film of the second thickness formed thereon and the high-voltage circuit portion has a third insulation film formed thereon which is greater in thickness than the first insulation film.
After a polysilicon layer is formed on the whole surface of the silicon substrate 1, the polysilicon layer and the second and third insulation films thereunder are patterned to selectively form gate electrodes and gate insulating films in both the low voltage and high-voltage circuit portions. FIG. 40 shows the state after the patterning, wherein in the low-voltage NMOS region LNR and the low-voltage PMOS region LPR, gate electrodes 51 and 52 respectively are formed on selectively formed gate insulating films 3 and in the high-voltage NMOS region HNR and the high-voltage PMOS region HPR, gate electrodes 53 and 54 respectively are formed on selectively formed gate insulating films 4.
In the step of FIG. 41, an N-type impurity such as arsenic (As) is ion implanted to a relatively low concentration into the surface of the silicon substrate 1 in the high-voltage NMOS region HNR, thereby to form a pair of extension layers 63. FIG. 41 shows that the upper portion other than that of the high-voltage NMOS region HNR is covered with a resist mask RM41 by photolithographic patterning and an N-type impurity is ion implanted into the high-voltage NMOS region HNR with the gate electrode 53 as an implant mask.
The pair of extension layers 63 are opposed to each other with the silicon substrate 1 under the gate electrode 53 sandwiched in between. In this case, an area of the silicon substrate 1 under the gate electrode 53 forms a channel region.
In the step of FIG. 42, a P-type impurity such as boron (B) is ion implanted to a relatively low concentration into the surface of the silicon substrate 1 in the high-voltage PMOS region HPR, thereby to form a pair of extension layers 64. FIG. 42 shows that the upper portion other than that of the high-voltage PMOS region HPR is covered with a resist mask RM42 by photolithographic patterning and a P-type impurity is ion implanted into the high-voltage PMOS region HPR with the gate electrode 54 as an implant mask.
The pair of extension layers 64 are opposed to each other with the silicon substrate 1 under the gate electrode 54 sandwiched in between. In this case, an area of the silicon substrate 1 under the gate electrode 54 forms a channel region.
In the step of FIG. 43, a silicon oxide film OX1 is formed to cover the whole surface of the silicon substrate 1. The silicon oxide film OX1 is then wholly etched back by anisotropic etching so as to leave the silicon oxide film OX1 only on the side surfaces of the gate electrodes 51 to 54 to form offset sidewalls 9.
In the step of FIG. 44, an N-type impurity such as arsenic (As) is ion implanted to a relatively low concentration into the surface of the silicon substrate 1 in the low-voltage NMOS region LNR, thereby to form a pair of extension layers 61. FIG. 44 shows that the upper portion other than that of the low-voltage NMOS region LNR is covered with a resist mask RM43 by photolithographic patterning and an N-type impurity is ion implanted into the low-voltage NMOS region LNR with the gate electrode 51 and the offset sidewall 9 as implant masks.
The pair of extension layers 61 are opposed to each other with the silicon substrate 1 under the gate electrode 51 sandwiched in between. In this case, an area of the silicon substrate 1 under the gate electrode 51 forms a channel region.
In the step of FIG. 45, a P-type impurity such as boron (B) is ion implanted to a relatively low concentration into the surface of the silicon substrate 1 in the low-voltage PMOS region LPR, thereby form a pair of extension layers 62. FIG. 45 shows that the upper portion other than that of the low-voltage PMOS region LPR is covered with a resist mask RM44 by photolithographic patterning and a P-type impurity is ion implanted into the low-voltage PMOS region LPR with the gate electrode 52 and the offset sidewall 9 as implant masks.
The pair of extension layers 62 are opposed to each other with the silicon substrate 1 under the gate electrode 52 sandwiched in between. In this case, an area of the silicon substrate 1 under the gate electrode 52 forms a channel region.
In the step of FIG. 46, after an insulation film such as silicon nitride film is formed to cover the whole surface of the silicon substrate 1, the silicon nitride film is wholly etched back by anisotropic etching to form sidewall insulating films 11 on the side surfaces of the offset sidewalls 9.
Thereafter, in the low-voltage NMOS region LNR, using the gate electrode 51, the offset sidewall 9 and the sidewall insulating film 11 as implant masks, an N-type impurity is ion implanted to a relatively high concentration to form a pair of source/drain layers 81. In the low-voltage PMOS region LPR, using the gate electrode 52, the offset sidewall 9 and the sidewall insulating film 11 as implant masks, a P-type impurity is ion implanted to a relatively high concentration to form a pair of source/drain layers 82.
In the high-voltage NMOS region HNR, using the gate electrode 53, the offset sidewall 9 and the sidewall insulating film 11 as implant masks, an N-type impurity is ion implanted to a relatively high concentration to form a pair of source/drain layers 83. In the high-voltage PMOS region HPR, using the gate electrode 54, the offset sidewall 9 and the sidewall insulating film 11 as implant masks, a P-type impurity is ion implanted to a relatively high concentration to form a pair of source/drain layers 84.
Through the aforementioned steps, the semiconductor device with the CMOS transistors 90A and 90B can be obtained.
In conventional techniques, as above described, although the extension layers in the low-voltage circuit portion and those in the high-voltage circuit portion have been formed in different steps, impurity ion implantations into the PMOS transistor and the NMOS transistor for formation of the extension layers have been performed under the same implant conditions.
Thus, the degrees of gate overlaps of the extension layers vary between the NMOS transistor and the PMOS transistor depending on a difference in diffusion rate in the silicon substrate between the N-type impurity (As) and the P-type impurity (B).